Increase in integration in semiconductor devices throughout recent years has invited reduction in line width of the semiconductor devices. In manufacturing such semiconductor devices with steppers, front surfaces of semiconductor wafers (i.e., exposure surfaces) are required to be highly flat.
The standard for evaluating the flatness has been hitherto GBIR (global back ideal range), a global standard, and SBIR (site back ideal range), a local standard. In recent years, semiconductor wafers are evaluated based on SFQR (site front-surface referenced least squares/range), a standard of the flatness in which focusing capabilities of the stepper over the whole segment regions of semiconductor wafer surfaces are considered.
According to a known proposal for a method of manufacturing semiconductor wafers capable of enhancing such SFQR, the relationship between the thickness of the carrier and the thickness of an unprocessed semiconductor wafer is defined during polishing by the double-side polishing machine, and a predetermined polishing allowance is secured, thereby enhancing SFQR (e.g., see Patent Document 1).
Patent Document 1: JP-A-2000-235941 (paragraph [0006])